For further information please fill the details below:

First Name
Last Name
Mobile Number
Email Address
Program Enquired
School Enquired
Home >

Dr. Basant K Mohanty

Associate Dean (Research) & Professor
Head of Department, Electronics and Telecommunication, MechatronicsPh.D. (VLSI for Signal Processing)

basant-mohanty

Areas of Specialisation

VLSI for Digital Signal Processing

Post-doctoral Research:

SCE, Nanyang Technological University, Singapore, 2014-2015

Qatar University, Doha, Qatar, 2012.

Work experience 

26 years

Professional Membership

  • Senior Member, IEEE
  • Life Member, IETE

Awards & Achievements:

  • Research Fellowship, Nanayang Technological University, Singapore
  • Research Fellowship from Qatar University, Qatar.
  • Received Rashtriya Gaurav Award, (2012) conferred by India International Friendship Society, New Delhi.

Publications:

Refereed Journals (SCI and SCOPUS Indexed)

  • B. K. Mohanty and P.K.Meher, "Area-Delay-Energy Efficient VLSI Architecture for Scalable In-place Computation of FFT on Real Data”, ”, IEEE Transaction on Circuits and Systems-I, Regular Papers, ISSN- 15498328, Vol.66, No.3, pp.1042-1050, Mar. 2019. Citation index/Citation per doc: 3.653, SNIP: 1.916, SJR: 1.269, Impact Factor: 2.83, H- Index: 99, SCI
  • B.K.Mohanty, "An efficient fixed-width adder-tree design using approximate computation”, IEEE Transaction on Circuits and Systems-II, Express Briefs, ISSN: 15497747, Vol.66, No.2, pp.192-196, Feb.2019, Citation index/Citation per doc: 2.124, SNIP: 1.702, SJR: 0.626, Impact Factor: 2.45, H- Index: 72, SCI
  • A. Choubey, and B. K. Mohanty, "Novel Data Access Scheme and Efficient Parallel Architecture for Multilevel 2-D DWT,” Circuits, Systems, and Signal Processing, Springer, ISSN- 0278081X, DOI: 10.1007/s00034-018-0775-y, Vol.37, No.10, pp.4482-4503, Oct. 2018, Citation index/Citation per doc: 1.777, SNIP: 1.004, SJR: 0.563, Impact Factor: 1.694, H- Index: 38, Google Citation: 0; SCI.
  • Vasundara, B. K. Mohanty, G. Panda and N. B. Puhan, "Hardware design for VLSI implementation of acoustic feedback canceller in hearing aids”, Circuit, Systems and Signal Processing, Regular Papers. ISSN- 0278081X, DOI: 10.1007/s00034-017-0619-1, Vol. 37, pp.1383-1406, Mar 2018, Citation index/Citation per doc: 1.777, SNIP: 1.004, SJR: 0.563, Impact Factor: 1.694, H- Index: 38, SCI.
  • B. K. Mohanty and Abhisek Choubey, "Efficient design for Radix-8 Booth Multiplier and its application inlifting 2-D DWT”, Circuit, Systems and Signal Processing, Regular Papers. ISSN- 0278081X, Vol.36, No.3, pp-1129-1149, Mar, 2017, Citation index/Citation per doc: 1.777, SNIP: 1.004, SJR: 0.563, Impact Factor: 1.694, H- Index: 38, SCI.
  • B. K. Mohanty, G. Singh, and G. Panda, "Hardware design for VLSI implementation of FxLMS and FsLMS based active noise controllers”, Circuits Systems and Signal Processing, Regular Papers, ISSN- 0278081X, Vol.36, No.2, pp. 447-473, Feb. 2017, Citation index/Citation per doc: 1.777, SNIP: 1.004, SJR: 0.563, Impact Factor: 1.694, H- Index: 38, SCI.
  • B. K. Mohanty, P.K.Meher and S. K. Patel, "LUT optimization for distributed arithmetic based block least mean square adaptive filter”, IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Regular Papers, , ISSN-10638210, Vol.24, No.5, pp.1926-1935, May 2016, Citation index/Citation per doc: 2.117, SNIP: 1.777, SJR: 0.447, Impact Factor: 1.698, H- Index: 85, SCI.
  • B. K. Mohanty, P.K.Meher, S.K.Singhal, and M.N.S.Swamy, "A High-Performance VLSI Architecture for Reconfigurable FIR using Distributed Arithmetic”, Integration, the VLSI Journal, Elsevier, ISSN- 01679260, Vol.54, pp. 37-46, June 2016, Citation index/Citation per doc: 1.347, SNIP: 1.019, SJR: 0.241, Impact Factor: 1.000, H- Index: 30, SCI.
  • S.K.Singhal and B. K. Mohanty "Efficient parallel architecture for fixed-coefficient and variable-coefficient FIR filters using distributed arithmetic”, Journal of Circuits, Systems, and Computers (JCSC), ISSN-02181266, Vol. 25, No. 7, pp. 1650073-1-1650073-19, March 2016, Citation index/Citation per doc: 0.509, SNIP: 0.337, SJR: 0.184, Impact Factor: 1.000, H- Index: 22, SCI.
  • B. K. Mohanty and P.K.Meher, "A high-performance FIR filter architecture for fixed and reconfigurable applications”, IEEE Transaction on Very Large Scale Integration (VLSI) Systems. ISSN-10638210, Vol. 24, No.2, pp. 444-452, Feb. 2016, Citation index/Citation per doc: 2.117, SNIP: 1.777, SJR: 0.447, Impact Factor: 1.698, H- Index: 85, SCI.
  • B. K. Mohanty and S.K.Singhal, "Area-delay and energy-efficient architecture for VLSI implementation of SDR channnelizer”, Circuit, Systems and Signal Processing, Vol. 35, No. 88, pp. 2958-2971, October, 2016, Citation index/Citation per doc: 1.777, SNIP: 1.004, SJR: 0.563, Impact Factor: 1.694, H- Index: 38, SCI.
  • B. K. Mohanty and S.K.Singhal, "Area-delay and energy-efficient architecture for VLSI implementation of SDR channnelizer”, Circuit, Systems and Signal Processing, Vol. 35, No. 88, pp. 2958-2971, October, 2016, Citation index/Citation per doc: 1.777, SNIP: 1.004, SJR: 0.563, Impact Factor: 1.694, H- Index: 38, SCI.
  • P.K.Meher, B. K. Mohanty, S. Patel, S.Ganguly and T. Srikanthan, "Efficient VLSI architecture for decimation-in-time fast Fourier transform of real-valued data”, IEEE Transaction on Circuits and Systems-I, Regular Papers, ISSN- 15498328, vol.62, no.12, pp.2836-2845, Dec.2015. Citation index/Citation per doc: 3.653, SNIP: 1.916, SJR: 1.269, Impact Factor: 2.407, H- Index: 99, SCI.
  • B.K.Mohanty and S. K. Patel, "Efficient very large scale integration architecture for variable length block least mean square adaptive filter”, IET Signal Processing,. DOI:10.1049/iet-spr.2014.0424, ISSN 17519683, Vol.9, No.8, pp.605-610, October 2015, Citation index/Citation per doc: 1.523, SNIP: 1.000, SJR: 0.458, Impact Factor: 1.298, H- Index: 28, SCI.
  • H.Rabah, A. Amira, B. K. Mohanty, S. Maadeed, and P. K.Meher, "FPGA Implementation of Orthogonal Matching Pursuit for Compressive Sensing Reconstruction, IEEE Transaction on Very Large Scale Integration (VLSI) Systems, ISSN-10638210, Vol. 62, No.1, pp. 2209-2220, Oct. 2015, Citation index/Citation per doc: 2.117, SNIP: 1.777, SJR: 0.447, Impact Factor: 1.698, H- Index: 85, SCI.
  • B. K. Mohanty, "Novel block formulation and area-delay-efficient reconfigurable interpolation FIR filter architecture for multi-standard SDR applications”, IEEE Transaction on Circuits and Systems-1, Regular Papers. ISSN- 15498328, Vol. 62, No.1, pp.283-291, Jan. 2015. Citation index/Citation per doc: 3.653, SNIP: 1.916, SJR: 1.269, Impact Factor: 2.407, H- Index: 99, SCI.
  • B.K.Mohanty and Vikas Tiwari, "Modified probabilistic estimation bias formulation for hardware efficient fixed-width Booth multiplier”, Circuit, Systems and Signal Processing, Springer, Vol.33, No.12, 3981-3994, Dec., 2014, Citation index/Citation per doc: 1.777, SNIP: 1.004, SJR: 0.563, Impact Factor: 1.694, HIndex: 38, Google Citation: 2; SCI.
  • B. K. Mohanty and S. K. Patel, "Area-delay-power efficient carry select adder”, IEEE Transaction on Circuits and Systems-II, Express Brief, ISSN: 15497747, Vol.61, No.6, pp.418-422, Jun. 2014, Citation index/Citation per doc: 2.124, SNIP: 1.702, SJR: 0.626, Impact Factor: 1.66, H- Index: 72, SCI.
  • B. K. Mohanty and P.K.Meher, "Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet transform by multiple lifting computation”, IET Image Processing, Vol.8, No.6, pp. 345-353, June 2014, ISSN: 17519659, Citation index/Citation per doc: 1.426, SNIP: 0.945, SJR: 0.322, Impact Factor: 1.044, H- Index: 26, SCI.
  • P.K.Meher, S.Y.Park, B. K. Mohanty, L.K.Seong and Y. C. Hao, "Efficient integer DCT architecture for HEVC”, IEEE Transaction on Circuits and Systems for Video Technology, ISSN: 10518215, Vol.24, No.1, pp.168-178, Jan. 2014, Citation index/Citation per doc: 5.663, SNIP: 1.916, SJR: 1.071, Impact Factor: 2.599, H- Index: 148, SCI.
  • B. K. Mohanty, P.K.Meher, S.A.Madeed, and A.Amira, "Memory footprint reduction for power-efficient realization of 2-D finite impulse response filters”, IEEE Transaction on Circuits and Systems-I, Regular Papers, ISSN: 15498328, Vol.61, No.1, pp.120-133, Jan. 2014, Citation index/Citation per doc: 3.612, SNIP: 1.916, SJR: 1.225, Impact Factor: 2.407, H- Index: 99, SCI.
  • B. K. Mohanty and Anurag Mahajan, "Scheduling Scheme and parallel architecture for computation of multilevel lifting 2-D DWT without using frame-buffer”, IET, Circuit, Device and Systems, ISSN: 1751858X, Vol.7, No.6, pp.319-325, Nov. 2013, Citation index/Citation per doc: 1.139, SNIP: 0.803, SJR: 0.264, Impact Factor: 1.092, H- Index: 40, SCI.
  • B. K. Mohanty and Anurag Mahajan, "Efficient-Block-Processing Parallel Architecture for Multilevel Lifting 2-D DWT”, ASP Journal of Low-power Electronics, Vol.9, No.1, pp.1-8, April 2013, ISSN: 15461998, SNIP: 0.388, SJR: 0.21, Impact Factor: 0.62, H- Index: 11, SCOPUS.
  • B. K. Mohanty and P.K.Meher, Memory-efficient high-speed convolution-based generic structure for multilevel 2-D DWT”, IEEE Transaction on Circuit and System for Video Technology, Vol.23, No.2, pp.353-363, Feb.2013. ISSN: 10518215, Citation index/Citation per doc: 5.100, SNIP: 1.916, SJR: 1.158, Impact Factor: 2.599, H- Index: 148, SCI
  • B.K.Mohanty and P.K.Meher, "A high-performance architecture for FIR adaptive filter based on a new distributed-arithmetic formulation of block least mean square algorithm”, IEEE Transaction on Signal Processing, Vol.61, no.4, pp. 921-932, Feb. 2013. ISSN: 1053587X, Citation index/Citation per doc: 5.264, SNIP: 2.587, SJR: 1.591, Impact Factor: 4.3, H- Index: 207, SCI
  • G.S.Maharana, P.K.Meher and B. K. Mohanty, "Efficient systolic architecture for VLSI realization of Heartly-like transforms”, International Journal of Computers and Application, Vol.35, No.1, pp.1-7, Feb. 2013, ISSN: 1206212X, SNIP: 0.240, SJR: 0.14, Impact Factor:0.13,H- Index: 9, SCOPUS
  • B. K. Mohanty, Anurag Mahajan and P.K.Meher, "Area-power-efficient high-throughput implementation of lifting 2-D DWT”, IEEE Transaction on Circuit and System-II, Express Brief. Vol.59, no.7, pp.434-438, July 2012, ISSN: 15497747, Citation index/Citation per doc: 2.124, SNIP: 1.702, SJR: 0.626, Impact Factor: 1.66, H- Index: 72, SCI.
  • B.K.Mohanty and P.K.Meher, Memory-efficient architecture for 3-D DWT using overlapped grouping of frames, IEEE Transaction on Signal Processing, Vol.59, No.11, pp. 5605-5616, Nov 2011, ISSN: 1053587X, Citation index/Citation per doc: 5.264, SNIP: 2.587, SJR: 1.591, Impact Factor: 4.3, HIndex: 207, Google Citation: 10; SCI
  • B. K. Mohanty and P.K.Meher, "Memory-efficient modular VLSI architecture for high-throughput and lowlatency implementation of multilevel lifting 2-D DWT, IEEE Transaction on Signal Processing, Vol.59, No.5, pp.2072-2084, May 2011, ISSN: 1053587X, Citation index/Citation per doc: 5.264, SNIP: 2.587, SJR: 1.591, Impact Factor: 4.3, H- Index: 207, SCI.
  • B. K. Mohanty and P.K.Meher, "Parallel and pipeline architecture for high-throughput computation of 3-D DWT, Regular Paper, IEEE Transaction on Circuit and System for Video Technology, Vol.20, No.9, pp.1200-1209, Sept. 2010. ISSN: 10518215, Citation index/Citation per doc: 3.632, SNIP: 1.916, SJR: 1.279, Impact Factor: 2.599, H- Index: 148, SCI.
  • P.K.Meher, B. K. Mohanty and J.C.Patra, "Hardware-Efficient Systolic-Like Modular Design for Two- Dimensional Discrete Wavelet Transform”, IEEE Transaction on Circuit and System -II, Express Briefs, Vol.55, No.2, pp.151-154, Feb. 2008, ISSN: 15497747, Citation index/Citation per doc: 2.124, SNIP: 1.702, SJR: 0.626, Impact Factor: 1.66, H- Index: 72, SCI.
  • B. K. Mohanty and P.K.Meher: "High-throughput and low-latency implementation of bit-level systolic architecture for 1-D and 2-D digital filters”, IET Computer and Digital Technique, Vol. 146, No. 2, pp. 91- 99, March 1999. ISSN: 17518601, Citation index/Citation per doc: 1.099, SNIP: 0.722, SJR: 0.210, Impact Factor: 0.515, H- Index: 38, SCI.
  • B. K. Mohanty and P.K.Meher: "Cost-effective novel flexible cell-level systolic architecture for high throughput implementation of 2-D FIR filter”, IET Computer and Digital Technique, Vol. 143, No.6, pp.436-439, Nov. 1996, ISSN: 17518601, Citation index/Citation per doc: 1.099, SNIP: 0.722, SJR: 0.210, Impact Factor: 0.515, H- Index: 38, SCI.

Refereed Journal (National)

  • B. K. Mohanty and P.K.Meher: "Novel flexible systolic mess architecture for parallel VLSI implementation of finite digital convolution”, IETE Journal of Research, Vol. 44, No.6, pp.261-266 Nov. 1998. ISSN: 03772063, Citation index/Citation per doc: 0.752, SNIP: 0.443, SJR: 0.168, Impact Factor: 0.909, H-index: 16, SCI 

Other Journals

  • A. Choubey and B. K. Mohanty, "A Block Based Area- Delay Efficient Architecture for Multi-level Lifting 2-D DWT,” International Journal of Computer Applications”, ISSN: 0975 – 8887, Vol. 169, No.4, July 2017.
  • V. Tiwari and B. K. Mohanty, Area-delay efficient flipping 2-d DWT structure using PEB Booth multiplier” International Journal of Computer Application, ISSN: 0975 – 8887, vol.146, no.13, pp. 36-38, July 2016. ISSN: 0975 – 8887, 

Papers Presented in National/International Conferences

  • B.K.Mohanty, Vivek Chaturvedi, Vijeta Rathore, and T.Srikanthan, "Memory-Access Aware Work-Load Distribution for Peak-Temperature Reduction of 3D Multi-core Embedded Systems”, IEEE International Conference on Digital Signal Processing, Singapore, July 2015, pp.1270-1277. DOI: 10.1109/ICDSP.2015.7252085
  • Vivek Chaturvedi, B.K.Mohanty, and T.Srikanthan, "Leakage-Aware Intra-Task Dynamic Voltage Scaling Technique for Energy Reduction in Real-Time Embedded Systems”, IEEE International Conference on Digital Signal Processing, Singapore, July 2015, pp.1266-1269. DOI: 10.1109/ICDSP.2015.7252084
  • Carlo Safarian, T.Ogunfunmi, W.J.Kojacky and B.K.Mohanty, "FPGA implementation of LMS-based FIR adaptive filter for real-time digital signal processing applications”, IEEE International Conference on Digital Signal Processing, Singapore, July 2015, pp.1251-1254. DOI: 10.1109/ICDSP.2015.7252081
  • B.K.Mohanty, P.K.Meher, and T. Srikanthan, "Critical-path optimization for efficient hardware realization of lifting and flipping DWTs”, IEEE International Symposium on Circuits and Systems (ISCAS-2015), pp.1186-1189, May 2015, Portugal, DOI: 10.1109/ISCAS.2015.7168851
  • P.K.Meher, B.K.Mohanty, and M.N.S.Swamy, "Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT using 9/7 and 5/3 Filters, 28 International Conference on VLSI Design, (VLSI-2015), pp.527-533, Bangaluru, India, 3-7 January 2015, DOI: 10.1109/VLSID.2015.61
  • P.K.Meher, B.K.Mohanty and T. Srikanthan, "Area-Delay Efficient Architecture for MP Algorithm Using Reconfigurable Inner-Product Circuits”, IEEE International Symposium on Circuits and Systems (ISCAS-2014), pp.2628-2631, May 2014, Australia, DOI: 10.1109/ISCAS.2014.6865712
  • B.K.Mohanty, S.A.Madeed, and A.Amira, "Systolic architecture for hardware efficient implementation of 2-D non-separable filter bank, In.Proc. International Design and Testing Symposium, Doha, Qatar, Dec.2012, DOI: 10.1109/IDT.2013.6727130
  • B.K.Mohanty, P.K.Meher and Subodh Singhal, "Efficient architectures for implementation of 2-D discrete Hadamard transform”, In Prco. IEEE International Symposium on Circuits and Systems, ISCAS 2012, pp.1480-1483, Seoul, South Korea, May 2012, DOI: 10.1109/ISCAS.2012.6271527
  • Anurag Mahajan and B.K.Mohanty, Efficient VLSI architecture for implementation of 1-D discrete wavelet transform based on distributed arithmetic, In Proc. IEEE Asia Pacific Conference on Circuit and Systems, APCCAS-2010, pp. 1195-1198, Malaysia, Dec 5-9, 2010, DOI: 10.1109/APCCAS.2010.5775015
  • B. K.Mohanty and P.K.Meher, "Efficient multiplier-less design for 1-D DWT using 9/7 filters based on distributed arithmetic,” IEEE International Symposium on Integrated Circuits (ISIC-2009), pp.364-367, 14-15 Dec, Singapore, 2009, EID: 2-s2.0-77950393791
  • B. K.Mohanty and P.K.Meher , "DA based bit-serial systolic architecture for 2-D non-separable discrete wavelet transform,” IEEE International Symposium on Integrated Circuits (ISIC-2009), pp.159-162, 14-15 Dec, Singapore, 2009, EID: 2-s2.0-77950446323
  • B.K.Mohanty and P.K.Meher, "New scan method and pipeline architecture for VLSI implementation of separable 2-D FIR filters without using transposition,” IEEE Region 10 TENCON2008 Conference, Hyderabad, 2008, DOI: 10.1109/TENCON.2008.4766758
  • B.K.Mohanty and P.K.Meher, "Delayed block LMS algorithm and concurrent architecture for high-speed implementation of adaptive FIR filters,” IEEE Region 10 TENCON2008 Conference, Hyderabad, Nov. 2008, DOI: 10.1109/TENCON.2008.4766786
  • B.K.Mohanty and P.K.Meher, "Concurrent systolic architecture for high-throughput implementation of 3-Dimensional discrete wavelet transform”, 19th IEEE International Conference Application-specific Systems, Architectures and Processors, ASAP'08, pp. 168-172, Belgium, 2008, DOI: 10.1109/ASAP.2008.4580172
  • B.K.Mohanty and P.K.Meher , "Throughput-Scalable Hybrid-Pipelined architecture for multilevel lifting 2-D DWT of JPEG 2000 Coder”, 19th IEEE International Conference Application-specific Systems, Architectures and Processors, ASAP'08, pp. 311-315, Belgium, July 2008, DOI: 10.1109/ASAP.2008.4580196
  • B. K. Mohanty and P. K. Meher "Memory-Efficient DA-Based Systolic Architecture for High-Speed Implementation of FIR Filters, IEEE International Workshop on Digital infoTainment and Visualization, IWDTV'08, Singapore, June 2008
  • B.K.Mohanty and Anurag Mahajan "CSE and CSD based systolic design for low-complexity VLSI implementation of 1-D DWT”, National Conference on Communication System and Networking, CSN-08, JIET, Guna, 2008.
  • B. K.Mohanty and P.K.Meher, Bit-serial systolic architecture for 2-D non-separable discrete wavelet transform, IEEE International Conference on Intelligent and Advanced Systems (ICIAS-2007), pp.1355-1358, Malaysia. May 2007, DOI: 10.1109/ICIAS.2007.4658605
  • B.K.Mohanty and P.K.Meher, "Pipelined architecture for high-speed implementation of multilevel lifting 2-D DWT using 9/7 filters, IEEE International Symposium on Signal Circuit and Systems, ISSCS2007, pp.137-140, July, Romania, July 2007, DOI: 10.1109/ISSCS.2007.4292670
  • B.K.Mohanty and P.K.Meher, "Merged-Cascaded Systolic Array for VLSI Implementation of Discrete Wavelet Transform” IEEE Asia Pacific Conference on Circuit and Systems, APCCAS-2006, pp.462-465, Singapore, 2006, DOI: 10.1109/APCCAS.2006.342489
  • B.K.Mohanty and P.K.Meher "VLSI Architecture for High-Speed/Low-Power Implementation of Multilevel Lifting DWT” IEEE Asia Pacific Conference on Circuit and Systems APCCAS-2006, pp. 458-461, Singapore, 2006, DOI: 10.1109/APCCAS.2006.342488
  • B.K.Mohanty and P.K.Meher "Bi-layer systolic architecture for bit-serial implementation of Discrete Wavelet Transform”, 10th IEEE International Conference on Communication Systems ICCS 2006, Singapore, 2006, DOI: 10.1109/ICCS.2006.301395
  • B.K.Mohanty and P.K.Meher, "Systolic architecture for transposition free VLSI implementation of 2-D DWT”, 10th IEEE International Conference on Communication Systems ICCS 2006, Singapore, 2006, DOI: 10.1109/ICCS.2006.301398
  • B.K.Mohanty: "Recursive Relation and Systolic Architecture for VLSI Implantation of Digit Serial Multiplier”, In Proc. Third National Conference on Applicable Mathematics in Wave Mechanics and Vibrations (WMVC-2006), Oct. 2006, Guna.
  • B.K.Mohanty: "Improved systolic architecture for non-separable two-dimensional discrete wavelet transform”, Accepted at World Informatika Conference, WEC’05 in Prague, Czech Republic, August 26-2, 2005.
  • B.K.Mohanty: "Digit-serial architectures for VLSI implementation of DLMS adaptive FIR filters”, Accepted at WSEAS 2004 Conferences in Salzburg, AUSTRIA, February 13-15, 2004, (http://www.wseas.us/e-library/conferences/austria2004/papers/482-302.pdf).

Google Scholar Citations: 

https://scholar.google.com/citations?hl=en&user=RQk2CZQAAAAJ

Professional Activity:

  • Associate Editor, (2012 onwards), Journal of Circuit, System and Signal Processing, Springer, Impact Factor: 1.697.
  • Reviewer in 15 SCI Journals including 7 IEEE Transactions.

Seminars/ Workshops/Conferences Attended/ Publications

  • IEEE International Design and Testing Symposium, organized by Texas A&M University, Doha, Qatar, Dec. 2012.
  • IEEE Region 10 TENCON 2008 Conference, Organized by University of Hyderabad, Nov.2008. 
  • 10th IEEE International Conference on Communication Systems 2006, Organized by Nanayang Technological University in Association with IEEE Singapore Section, Singapore, Oct 2006.
  • IEEE International Conference on Signal Processing and Communication, Jointly organized by JIIT, Noida and IEEE Delhi Section, 2013.
  • International Conference on Signal Processing, (ICSPSATI-2016), Nov.7, 2016, Samrat Ashok Technological Institute (SAATI), Vidisha, Madhya Pradesh.
  • 1-Day workshop on "Project proposal preparation” organized by MPCST, Bhopal, March 7, 2017

Official Email Id

basantkumar.mohanty@nmims.edu

           
© Copyright 2019. Shri Vile Parle Kelavani Mandal (SVKM) All Rights Reserved.   Disclaimer  |  Privacy Policy
TOP